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Preliminary
74LVTH16835 Low Voltage 18-Bit Universal Bus Driver
May 2000 Revised May 2000
74LVTH16835 Low Voltage 18-Bit Universal Bus Driver with 3-STATE Outputs (Preliminary)
General Description
The LVTH16835 consists of 18-bit universal bus drivers which combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. Data flow from A to Y is controlled by the output-enable (OE) input. This device operates in the transparent mode when the latch-enable (LE) input is HIGH. The A data is latched if the clock (CLK) input is held at a HIGH or LOW logic level. If LE is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of the CLK. When OE is HIGH, the outputs are in the high-impedance state. The LVTH16835 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The bus driver is designed for low voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16835 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number 74LVTH16835MEA 74LVTH16835MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2000 Fairchild Semiconductor Corporation
DS500102
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Preliminary 74LVTH16835 Connection Diagram Pin Descriptions
Pin Names A1-A18 Y1-Y18 CLK OE LE Description Data Register Inputs 3-STATE Outputs Clock Pulse Input Output Enable Input Latch Enable Input
Truth Table
Inputs OE H L L L L L L LE X H H L L L L CLK X X X H L A X L H L H X X Output Y Z L H L H Y0 (Note 1) Y0 (Note 2)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = HIGH-to-LOW Clock Transition Note 1: Output level before the indicated steady-state input conditions were established, provided that CLK was HIGH before LE went LOW. Note 2: Output level before the indicated steady-state input conditions were established.
Logic Diagram
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Preliminary
74LVTH16835
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value -0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50 64 128 64 128 -65 to +150 Output in 3-STATE Output in HIGH or LOW State (Note 4) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State Conditions Units V V V V mA mA mA mA mA C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA t/V Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V -40 0 Parameter Min 2.7 0 Max 3.6 5.5 -32 64 85 10 Units V V mA mA C ns/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed.
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Preliminary 74LVTH16835 DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) II(OD) II Bushold Input Minimum Drive Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH+ ICCH ICCL ICCZ ICCZ+ ICC Power Off Leakage Current Power up/down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 7)
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
T A = -40C to +85C Min 2.0 0.8 VCC - 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 75 -75 500 -500 10 1 -5 1 100 100 -5 5 10 0.19 5 0.19 0.19 0.2 Max -1.2
Units V V V V V V V V V V A A A A A A A A A A A A A mA mA mA mA mA
Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 5) (Note 6) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.5V VO = 3.0V VCC < VO 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC VO 5.5V, Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
3.0 3.0 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 8)
TA = 25C Conditions Max Units V V CL = 50 pF, RL = 500 (Note 9) (Note 9)
Min
Typ 0.8 -0.8
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
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Preliminary
74LVTH16835
AC Electrical Characteristics
TA = -40C to +85C, CL = 50 pF, RL = 500 Symbol Parameter VCC = 3.3 0.3V Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tS Setup Time A before CLK A before LE, CLK HIGH A before LE, CLK LOW tH tW tOSLH tOSHL Hold Time Pulse Duration Output to Output Skew (Note 10) A after CLK A after LE LE HIGH CLK HIGH or LOW Output Disable Time Propagation Delay A to Y Propagation Delay LE to Y Propagation Delay CLK to Y Output Enable Time 150 1.3 1.3 1.5 1.5 1.5 1.5 1.3 1.3 1.7 1.7 2.1 2.3 1.5 1.0 0.8 3.3 3.3 1.0 1.0 3.7 3.7 5.1 5.1 5.1 5.1 4.6 4.6 5.8 5.8 Max VCC = 2.7V Min 150 1.3 1.3 1.5 1.5 1.5 1.5 1.3 1.3 1.7 1.7 2.4 1.5 0.5 0.0 0.8 3.3 3.3 1.0 1.0 ns ns ns ns 4.0 4.0 5.7 5.7 5.7 5.7 5.5 5.5 6.3 6.3 Max MHz ns ns ns ns ns Units
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 11)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VCC = 0V, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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Preliminary 74LVTH16835 Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A
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Preliminary
74LVTH16835 Low Voltage 18-Bit Universal Bus Driver
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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